The invention generally relates to semiconductor devices, and, more particularly, to transistors that include buried channel layers.
Certain microelectronics systems, such as radars, satellites, and cell phones, often require low-power, high-speed and high-density circuits having a high signal-to-noise ratio (i.e., low noise). These requirements present significant design challenges both at the circuit design and at the transistor design level.
Microelectronic devices that include both analog and digital circuits can fulfill all these requirements. Typically, analog circuits are used to satisfy very high speed and low noise requirements, while digital circuits are used to satisfy high density and low power requirements.
Microelectronic devices that include both analog and digital circuits on the same silicon substrate typically include surface channel metal oxide semiconductor field-effect transistors (MOSFET). Surface channel analog MOSFETs, however, incur noise problems because noise is induced at high frequencies due to charge carrier scattering along the silicon surface channel/gate oxide interface. Thus, for high-speed analog devices, bipolar transistors are often preferred over surface channel field-effect transistors (FETs); bipolar transistor-based circuits can exhibit lower noise because conduction does not occur along a semiconductor-insulator interface. Unfortunately, it is difficult to integrate both bipolar and surface channel MOSFET devices on a single substrate.
One way to reduce noise and to integrate digital and analog circuits is through use of both surface channel and buried channel transistors. A buried channel FET can have a channel conduction layer that is buried between doped silicon regions. A buried channel device can exhibit low noise because the conduction occurs in a layer that is spaced. e.g., from a silicon/SiO2 interface.
Current flow in a buried channel FET can be controlled by controlled doping of a hetero-semiconductor buried layer. The channel may be formed in a region that includes a narrow bandgap semiconductor. Alternatively, the buried layer can be a quantum well (typically, an ultra-thin layer of narrower bandgap semiconductor sandwiched between two layers of larger bandgap semiconductors).
The conductivity of the buried channel is also controlled by a gate bias voltage. In order to operate the transistor, the buried layer often requires doping control to assist population of the channel with free charge carriers.
Some buried channel transistors include a narrow bandgap InGaAs quantum well and an intermediate bandgap AlGaAs layer; the well is disposed beneath the heterointerface of the InGaAs single quantum well with a wide bandgap AlGaAs layer. A thin charge sheet having the same conductivity type as the wide bandgap layer is formed at the heterointerface. As the magnitude of the gate voltage increases, an enhanced concentration of free charge carriers in the quantum well may occur.
It has been found, however, that driving the gate voltage high enough to accomplish quantum well population typically creates a parallel conduction channel in the surface semiconductor layer, due to formation of an inversion region in the surface layer. The surface inversion layer again leads to noise problems since conduction can then appear at the semiconductor/oxide interface. The surface conduction path can also use excess power.
A further problem arises because buried channel devices often utilize advanced doping techniques to ensure that a quantum well is populated with charge carriers. To achieve the doping desired in the buried channel layer, the device layers above the buried channel are also partially doped, thus requiring a complex process of counter-doping device layers.
Relatively exotic ion implantation processes can be used to create effective buried channel devices. For example, a buried channel p-MOSFET device can utilize plasma-doping to fabricate a very shallow p-type channel layer on the top surface of a sub-micrometer buried channel p-MOSFET. The buried channel p-MOSFET device formed using this method has a higher current drivability and a higher anti-punchthrough resistance.
Moreover, it is difficult to provide enhanced current drive for both electrons and holes (i.e., n-type and p-type buried channel devices) on the same substrate due to added complexity in the semiconductor fabrication; the required ion implantations and counter-doping can demand intricate processing steps.
The invention involves semiconductor devices that include buried channel layers having heterojunction offsets, and involves the use of back-biasing to control free charge carrier density in a buried channel and a surface layer of the devices. Back-biasing is applied, for example, via substrate or body-biasing. Features of the invention provide, in particular, improved field-effect transistors that include, for example, a strained buried layer of silicon, germanium or SiGe.
The invention can provide, for example, lower noise, greater carrier mobility, and both p-channel and n-channel buried layer devices in a single integrated circuit. For example, a transistor according to the invention can have improved low-frequency noise (Flicker noise), for use in oscillator circuits. In particular, the invention can provide transistors well suited to subthreshold and analog operation. For example, the invention can provide analog and radio-frequency devices having transistors with increased transconductance, where a buried layer has carrier mobility superior to carrier mobility in a surface layer. The invention also provides simpler device manufacturing, and can eliminate a need for complex doping steps during fabrication.
In preferred embodiments, the invention entails devices that include buried strained-layer quantum wells within multi-layer heterostructures, and entails methods of using back-biasing to populate the buried layers. The back-bias voltage controls preferential population of charge carriers in the buried layer while leaving a surface layer relatively free of mobile charge carriers.
Thus, in a first aspect, the invention features a method for operating one or more transistors. The method includes providing a transistor, which includes a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate. The method also includes causing current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.
The back-bias voltage can substantially prevent formation of an inversion region in the surface layer. The back-bias voltage can be selected in cooperation with a gate voltage to cause radio-frequency operation of the transistor. A range of gate voltages can be selected to operate the transistor in a substantially linear drain current versus source voltage condition. The transistor can be operated as an analog device, for example, a power device.
The buried channel layer can include a semiconductor of different composition from neighboring, contiguous layers. The buried layer can be in direct contact with the surface layer, or with additional intermediate layers. The interface with a neighboring layer can provide a heterojunction offset. The offset can assist confinement of free charge carriers within the buried layer. The buried channel layer can be, for example, a quantum well.
The buried channel layer can include a strained semiconductor, and the surface layer can include a semiconductor that is substantially strain-free. The buried layer can reside on a relaxed layer, which can include silicon and germanium.
In some embodiments, the strained semiconductor is under tensile strain, and applying the back-bias voltage causes the buried channel layer to provide an n-type channel. The method can further include providing a second transistor associated with the first transistor. The second transistor includes a second buried channel layer, which includes a semiconductor under compressive strain. Applying a second back-bias voltage to the second transistor causes the second buried channel layer to provide a p-type channel.
The back-bias voltage in some embodiments is applied to a substrate, and in other embodiments is applied to an intermediate layer adjacent to the transistor.
In a second aspect, the invention features a semiconductor device. The device includes a transistor, which includes a buried channel layer and a surface layer. The device also includes a terminal facilitating application of a voltage to the gate to control a current between the source and the drain. The device includes a charge carrier modulator facilitating application of a back-bias voltage to the transistor. The back-bias voltage modulates the free charge carrier density distribution in the buried layer and in the surface layer. The modulation of the free charge carrier density distribution causes the current to flow predominately through the buried channel layer.
The buried channel layer can consist substantially of silicon or germanium, or can include silicon and germanium. The buried channel layer can include a semiconductor under compressive or tensile strain.